(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the gap filling and planarization characteristics of a dielectric layer in the fabrication of integrated circuits.
(2) Description of the Prior Art
Current practice for filling gaps between portions of a patterned metal layer involves using spin-on-glass or a high density plasma (HDP) oxide for gap filling followed by planarization such as by chemical mechanical polishing (CMP). A typical example is illustrated in FIGS. 1 through 3. Referring now to FIG. 1, there is illustrated a partially completed integrated circuit device. Semiconductor device structures such as gate electrode 14 and source and drain regions 16 have been fabricated in and on the semiconductor substrate 10, as is conventional in the art. A dielectric layer 18 has been deposited overlying the semiconductor device structures and planarized. A metal layer 20 has been deposited and patterned to form the desired metal pattern. The intermetal dielectric layer 22, such as silicon dioxide, is deposited conformally over the patterned metal layer 20. Spin-on-glass layer 24, for example, fills the gaps between the metal pattern.
Referring now to FIG. 2, the spin-on-glass layer 24 and the intermetal dielectric layer 22 are etched back. A second intermetal dielectric layer 26 is deposited over the etched back layers. An etch stop layer such as silicon nitride layer 28 may now be deposited followed by a glasseous layer such as phosphosilicate glass (PSG) layer 30. FIG. 3 illustrates the integrated circuit device after planarization by CMP.
The prior art process illustrated in FIGS. 1 through 3 has a number of drawbacks. There is little margin for the spin-on-glass etchback because the layer 22 has to be thin enough that it does not close at the top. Thinning of the dielectric film over wide trenches, called dishing, may occur and may effect final planarization if overpolished. This is because the polish rate for layer 30 is much faster than the polish rate for layer 28. Polishing of the layer 28 will slow down while the other areas are still being polished at a higher rate. Another drawback is that the stop layer 28 increases the capacitance in the circuit. Finally, the shape of the via etched through the PSG, etch stop, and second intermetal dielectric layers 30,28,26 is difficult to control because of the three different materials in these layers.
Co-pending U.S. patent application Ser. No. 08/650,694 (CS95-090) to J. Z. Zheng et al filed on May 20, 1995 teaches the use of titanium nitride, titanium tungsten, tungsten, and the like, as a polish stop layer. U.S. Pat. No. 5,262,348 to Bindal et al shows a method of forming nitride polish stops in the bottom of apertures. U.S. Pat. No. 5,362,669 to Boyd et al teaches forming a polish stop layer in the middle of a wide trench to prevent dishing. U.S. Pat. No. 5,324,690 to Gelatos et al teaches forming a ternary boron nitride film as a polish stop layer. U.S. Pat. No. 5,385,866 to Bartush teaches using an oxidized boron nitride polish stop layer. U.S. Pat. No. 5,246,884 to Jaso et al teaches a CVD diamond or diamond-like carbon polish stop layer.